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Type of non-planar transistor
A double-gate FinFET device
A fin field-effect transistor (FinFET) is a multigate device, a MOSFET (metal-oxide-semiconductor field-effect transistor) built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, forming a double or even multi gate structure. These devices have been given the generic name "FinFETs" because the source/drain region forms fins on the silicon surface. The FinFET devices have significantly faster switching times and higher current density than planar CMOS (complementary metal-oxide-semiconductor) technology.
It is common for a single FinFET transistor to contain several fins, arranged side by side and all covered by the same gate, that act electrically as one, to increase drive strength and performance.
The first FinFET transistor type was called a "Depleted Lean-channel Transistor" or "DELTA" transistor, which was first fabricated in Japan by Hitachi Central Research Laboratory's Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto and Eiji Takeda in 1989. The gate of the transistor can cover and electrically contact the semiconductor channel fin on both the top and the sides or only on the sides. The former is called a tri-gate transistor and the latter a double-gate transistor. A double-gate transistor optionally can have each side connected to two different terminal or contacts. This variant is called split transistor. This enables more refined control of the operation of the transistor.
Indonesian engineer Effendi Leobandung, while working at the University of Minnesota, published a paper with Stephen Y. Chou at the 54th Device Research Conference in 1996 outlining the benefit of cutting a wide CMOS transistor into many channels with narrow width to improve device scaling and increase device current by increasing the effective device width. This structure is what a modern FinFET looks like. Although some device width is sacrificed by cutting it into narrow widths, the conduction of the side wall of narrow fins more than make up for the loss, for tall fins. The device had a 35 nm channel width and 70 nm channel length.
The industry's first 25 nanometer transistor operating on just 0.7 volts was demonstrated in December 2002 by TSMC. The "Omega FinFET" design, named after the similarity between the Greek letter "Omega" and the shape in which the gate wraps around the source/drain structure, has a gate delay of just 0.39 picosecond (ps) for the N-type transistor and 0.88 ps for the P-type.
In 2004, Samsung demonstrated a "Bulk FinFET" design, which made it possible to mass-produce FinFET devices. They demonstrated dynamic random-access memory (DRAM) manufactured with a 90nm Bulk FinFET process.
In 2011, Intel demonstrated tri-gate transistors, where the gate surrounds the channel on three sides, allowing for increased energy efficiency and lower gate delay--and thus greater performance--over planar transistors.
Commercially produced chips at 22 nm and below have generally utilised FinFET gate designs (but planar processes do exist down to 18 nm, with 12 nm in development). Intel's tri-gate variant were announced at 22 nm in 2011 for its Ivy Bridge microarchitecture. These devices shipped from 2012 onwards. From 2014 onwards, at 14 nm (or 16 nm) major foundries (TSMC, Samsung, GlobalFoundries) utilised FinFET designs.
In 2013, SK Hynix began commercial mass-production of a 16nm process, TSMC began production of a 16nm FinFET process, and Samsung Electronics began production of a 10nm process. TSMC began production of a 7 nm process in 2017, and Samsung began production of a 5 nm process in 2018. In 2019, Samsung announced plans for the commercial production of a 3nm GAAFET process by 2021.
Bohr, Mark T.; Young, Ian A. (2017). "CMOS Scaling Trends and Beyond". IEEE Micro. 37 (6): 20-29. doi:10.1109/MM.2017.4241347. S2CID6700881. The next major transistor innovation was the introduction of FinFET (tri-gate) transistors on Intel's 22-nm technology in 2011.