Burst Mode (computing)
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Burst Mode Computing

Burst mode is a generic electronics term referring to any situation in which a device is transmitting data repeatedly without going through all the steps required to transmit each piece of data in a separate transaction.


The main advantage of burst mode over single mode is that the burst mode typically increases the throughput of data transfer. Any bus transaction is typically handled by an arbiter, which decides when it should change the granted master and slaves. In case of burst mode, it is usually more efficient if you allow a master to complete a known length transfer sequence.

The total delay in a data transaction can be typically written as a sum of initial access latency plus sequential access latency.

Here the sequential latency is same in both single mode and burst mode, but the total initial latency is decreased in burst mode, since the initial delay (usually depends on FSM for the protocol) is caused only once in burst mode. Hence the total latency of the burst transfer is reduced, and hence the data transfer throughput is increased.

It can also be used by slaves that can optimise their responses if they know in advance how many data transfers there will be. The typical example here is a DRAM which has a high initial access latency, but sequential accesses after that can be performed with fewer wait states.[1]


The usual reason for having a burst mode capability, or using burst mode, is to increase data throughput.[2] The steps left out while performing a burst mode transaction may include:

  • Waiting for input from another device
  • Waiting for an internal process to terminate before continuing the transfer of data
  • Transmitting information which would be required for a complete transaction, but which is inherent in the use of burst mode[3]

In the case of DMA, the DMA controller and the device are given exclusive access to the bus without interruption; the CPU is also freed from handling device interrupts.

The actual manner in which burst modes work varies from one type of device to another; however, devices that have some sort of a standard burst mode include the following:

See also


  1. ^ "ARM forums".
  2. ^ PCI Local Bus Specification Revision 2.2. Hillsboro, Oregon: PCI Special Interest Group. December 18, 1998. p. 82.
  3. ^ PCI Local Bus Specification Revision 2.2. Hillsboro, Oregon: PCI Special Interest Group. December 18, 1998. p. 29.

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