The 90 nm process refers to the level of MOSFET (CMOS) fabrication process technology that was commercialized by the 2003-2005 timeframe, by leading semiconductor companies like Toshiba, Sony, Samsung, IBM, Intel, Fujitsu, TSMC, Elpida, AMD, Infineon, Texas Instruments and Micron Technology.
The origin of the 90 nm value is historical, as it reflects a trend of 70% scaling every 2-3 years. The naming is formally determined by the International Technology Roadmap for Semiconductors (ITRS).
The 193 nm wavelength was introduced by many (but not all) companies for lithography of critical layers mainly during the 90 nm node. Yield issues associated with this transition (due to the use of new photoresists) were reflected in the high costs associated with this transition.
Even more significantly, the 300 mm wafer size became mainstream at the 90 nm node. The previous wafer size was 200 mm diameter.
Toshiba, Sony and Samsung developed a 90nm process during 2001-2002, before being introduced in 2002 for Toshiba's eDRAM and Samsung's 2Gb NAND flash memory. IBM demonstrated a 90nm silicon-on-insulator (SOI) CMOS process, with development led by Ghavam Shahidi, in 2002. The same year, Intel demonstrated a 90nm strained-silicon process. Fujitsu commercially introduced its 90nm process in 2003 followed by TSMC in 2004.
Gurtej Singh Sandhu of Micron Technology initiated the development of atomic layer deposition high-k films for DRAM memory devices. This helped drive cost-effective implementation of semiconductor memory, starting with 90nm node DRAM.
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