A more significant limitation comes from plasma damage to low-k materials. The extent of damage is typically 20 nm thick, but can also go up to about 100 nm. The damage sensitivity is expected to get worse as the low-k materials become more porous. For comparison, the atomic radius of an unconstrained silicon is 0.11 nm. Thus about 90 Si atoms would span the channel length, leading to substantial leakage.
Tela Innovations and Sequoia Design Systems developed a methodology allowing double exposure for the 16/14 nm node circa 2010.Samsung and Synopsys have also begun implementing double patterning in 22 nm and 16 nm design flows.Mentor Graphics reported taping out 16 nm test chips in 2010. On January 17, 2011, IBM announced that they were teaming up with ARM to develop 14 nm chip processing technology.
On February 18, 2011, Intel announced that it would construct a new $5 billion semiconductor fabrication plant in Arizona, designed to manufacture chips using the 14 nm manufacturing processes and leading-edge 300 mm wafers. The new fabrication plant was to be named Fab 42, and construction was meant to start in the middle of 2011. Intel billed the new facility as "the most advanced, high-volume manufacturing facility in the world," and said it would come on line in 2013. Intel has since decided to postpone opening this facility and instead upgrade its existing facilities to support 14-nm chips. On May 17, 2011, Intel announced a roadmap for 2014 that included 14 nm transistors for their Xeon, Core, and Atom product lines.
In the late 1990s, Hisamoto's Japanese team from Hitachi Central Research Laboratory began collaborating with an international team of researchers on further developing FinFET technology, including TSMC's Chenming Hu and various UC Berkeley researchers. In 1998, the team successfully fabricated devices down to a 17nm process. They later developed a 15nm FinFET process in 2001. In 2002, an international team of researchers at UC Berkeley, including Shibly Ahmed (Bangladeshi), Scott Bell, Cyrus Tabery (Iranian), Jeffrey Bokor, David Kyser, Chenming Hu (Taiwan Semiconductor Manufacturing Company), and Tsu-Jae King Liu, demonstrated FinFET devices down to 10 nm gate length.
In 2005, Toshiba demonstrated a 15 nm FinFET process, with a 15 nm gate length and 10 nm fin width, using a sidewall spacer process. It has been suggested that for the 16 nm node, a logic transistor would have a gate length of about 5 nm. In December 2007, Toshiba demonstrated a prototype memory unit that used 15-nanometre thin lines.
In December 2009, National Nano Device Laboratories, owned by the Taiwanese government, produced a 16 nm SRAM chip.
In September 2011, Hynix announced the development of 15 nm NAND cells.
In August 2014, Intel announced details of the 14 nm microarchitecture for its upcoming Core M processors, the first product to be manufactured on Intel's 14 nm manufacturing process. The first systems based on the Core M processor were to become available in Q4 2014 -- according to the press release. "Intel's 14 nanometer technology uses second-generation tri-gate transistors to deliver industry-leading performance, power, density and cost per transistor," said Mark Bohr, Intel senior fellow, Technology and Manufacturing Group, and director, Process Architecture and Integration.
In 2018 a shortage of 14 nm fab capacity was announced by Intel.
On September 25, 2015, Apple Inc. released the IPhone 6S and iPhone 6S Plus, which are equipped with "desktop-class" A9 chips that are fabricated in both 14 nm by Samsung and 16 nm by TSMC (Taiwan Semiconductor Manufacturing Company).
In June 2016, AMD released its Radeon RX 400 GPUs based on the Polaris architecture, which incorporates 14 nm FinFET technology from Samsung. The technology was licensed to GlobalFoundries for dual sourcing.
Lower numbers are better, except for transistor density, in which case is the opposite. Transistor gate pitch is also referred to as CPP (contacted poly pitch), and interconnect pitch is also referred to as MMP (minimum metal pitch).
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^Axelrad, V.; et al. (2010). "16nm with 193nm immersion lithography and double exposure". Proc. SPIE. 7641: 764109. doi:10.1117/12.846677.
^Noh, M-S.; et al. (2010). "Implementing and validating double patterning in 22-nm to 16-nm product design and patterning flows". Proc. SPIE. 7640: 76400S. doi:10.1117/12.848194.
^Kaneko, A; Yagashita, A; Yahashi, K; Kubota, T; et al. (2005). "Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm FinFET with elevated source/drain extension". IEEE International Electron Devices Meeting (IEDM 2005). pp. 844-847. doi:10.1109/IEDM.2005.1609488. Cite uses deprecated parameter |displayauthors= (help)